1. Field of the Invention
The invention relates to a clock data recovery (CDR) circuit and, in particular, to a clock data recovery (CDR) circuit with an LC gated VCO.
2. Description of the Related Art
Some digital data streams, especially high-speed serial data streams (such as a raw data stream from a magnetic head of a disk drive), are transmitted without an accompanying clock. A receiver generates a clock from an approximate reference clock frequency, and then phase-aligns to transitions in the data stream with a phase locked loop. This process is commonly known as clock and data recovery (CDR)
In optical point-to-multipoint communication systems, multi-Gb/s burst-mode clock and data recovery (CDR) circuit plays an important role. For passive optical network (PON) applications, each asynchronous packet has to be correctly received within several tens of bit times. Conventional phase-locked-loop (PLL)-based CDR circuits suffer from the long settling time. Accordingly, a high speed CMOS CDR circuit is highly demanded by a communication system designer.